----------------------------------------------------------
-- UNIX Modelsim Tutorial
--
-- Simple VHDL Testbench entity
--
-- Author : Ambarish Sule (amsule@unity.ncsu.edu)
---------------------------------------------------------- 

library ieee;  -- similar to #include in C
use ieee.std_logic_1164.all;

-- Declare the ports if any
entity test_top is
  -- No ports since this is a Testbench
end test_top;


architecture BEHAVIORAL of test_top is

  -- Describe the components that will be used
  component VER_DUV                     -- duv.v has this component's definition
    port (
      Ain  : in  std_logic;
      Bin  : in  std_logic;
      Cout : out std_logic);
  end component;
  --  Both Verilog and VHDL components are treated identically
  component VHDL_DUV                    -- duv.vhdl has this component's definition
    port (
      Ain  : in  std_logic;
      Bin  : in  std_logic;
      Cout : out std_logic);
  end component;

  -- Declare the internal signals in the Testbench
  signal AinVer, BinVer, CoutVer : std_logic;
  signal AinVhd, BinVhd, CoutVhd : std_logic;
  
begin  -- architecture BEHAVIORAL

  -- Instantiate the components that were described above
  UVER_DUV: VER_DUV                     -- UVER_DUV=Instance name,
                                        -- VER_DUV=Component name
    port map (
      Ain  => AinVer,                   -- Ain=port name, AinVer is the Signal
                                        -- connected in the Testbench
      Bin  => BinVer,
      Cout => CoutVer);

  --  Both Verilog and VHDL components are instantiated identically
  UVHDL_DUV: VHDL_DUV
    port map (
      Ain  => AinVhd,
      Bin  => BinVhd,
      Cout => CoutVhd);

  -- Start a process at time 0
  STIMULUS_VER : process
  begin  -- process STIMULUS
    AinVer<='0'; BinVer<='0';
    wait for 10 ns;
    AinVer<='0'; BinVer<='1';
    wait for 10 ns;
    AinVer<='1'; BinVer<='0';
    wait for 10 ns;
    AinVer<='1'; BinVer<='1';
    wait for 100 ns;
    -- The process will restart after 100 ns
  end process STIMULUS_VER;

  -- Start another process simultaneously at time 0
  STIMULUS_VHDL: process
  begin  -- process STIMULUS_VHDL
    AinVhd<='0'; BinVhd<='0';
    wait for 10 ns;
    AinVhd<='0'; BinVhd<='1';
    wait for 10 ns;
    AinVhd<='1'; BinVhd<='0';
    wait for 10 ns;
    AinVhd<='1'; BinVhd<='1';
    wait;                               -- Indefinite wait
    -- This process never restarts
  end process STIMULUS_VHDL;
  
end BEHAVIORAL; -- architecture BEHAVIORAL