Model { Name "blinky" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon Jun 24 10:33:52 2002" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "wdavis" ModifiedDateFormat "%" LastModifiedDate "Sat Jan 25 17:00:13 2003" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode45" SolverMode "Auto" StartTime "0.0" StopTime "10.0" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on ShowAdditionalParam off OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Inport Port "1" PortDimensions "-1" SampleTime "-1" ShowAdditionalParam off LatchInput off DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Terminator } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "blinky" Location [183, 119, 513, 319] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Constant Name "Constant" Position [60, 55, 90, 85] } Block { BlockType Scope Name "Scope" Ports [2] Position [235, 46, 265, 79] Location [188, 365, 512, 604] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } List { ListType SelectedSignals axes1 "" axes2 "" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" } Block { BlockType SubSystem Name "blinker" Tag "fpga30" Ports [1, 2] Position [135, 40, 175, 100] TreatAsAtomicUnit off System { Name "blinker" Location [180, 439, 840, 617] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "In1" Position [25, 38, 55, 52] } Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [141, 82, 192, 132] ShowName off AttributesFormatString "System\\nGenerator" SourceBlock "xbsBasic_r2/ System Generator" SourceType "Xilinx System Generator" xilinxfamily "Virtex2" part "xc2v1000" speed "-6" package "fg256" synthesis_tool "XST" directory "c:/temp/blinky/sysgen" testbench on simulink_period "1" sysclk_period "10" trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off } Block { BlockType Reference Name "Counter" Ports [1, 1] Position [285, 30, 325, 70] SourceBlock "xbsBasic_r2/Counter" SourceType "Xilinx Counter Block" cnt_type "Free Running" n_bits "26" bin_pt "0" arith_type "Signed (2's comp)" start_count "0" cnt_to "Inf" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en off trim_vbits on dbl_ovrd off gen_core on use_rpm off deprecated_control off } Block { BlockType Reference Name "Gateway In" Tag "rst" Ports [1, 1] Position [80, 34, 135, 56] SourceBlock "xbsIO_r2/Gateway In" SourceType "Xilinx Gateway In" arith_type "Boolean" n_bits "8" bin_pt "6" quantization "Truncate" overflow "Wrap" period "1" timing_constraint "None" locs_specified on LOCs "'M1'" needs_fixed_name off dbl_ovrd off } Block { BlockType Reference Name "Gateway Out" Tag "led" Ports [1, 1] Position [530, 39, 585, 61] SourceBlock "xbsIO_r2/Gateway Out" SourceType "Xilinx Gateway Out" hdl_port on timing_constraint "None" locs_specified on LOCs "'C13'" needs_fixed_name off } Block { BlockType Reference Name "Gateway Out1" Tag "led" Ports [1, 1] Position [530, 114, 585, 136] SourceBlock "xbsIO_r2/Gateway Out" SourceType "Xilinx Gateway Out" hdl_port on timing_constraint "None" locs_specified on LOCs "{'C16','E13','H14','H16'}" needs_fixed_name off } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [190, 27, 235, 63] SourceBlock "xbsMath_r2/Inverter" SourceType "Xilinx Inverter" latency "0" explicit_period off period "1" en off trim_vbits on dbl_ovrd off use_core on gen_core on use_rpm off deprecated_control off } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [400, 31, 440, 69] SourceBlock "xbsBasic_r2/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" trim_vbits on dbl_ovrd off deprecated_control off } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [400, 106, 440, 144] SourceBlock "xbsBasic_r2/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "4" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" trim_vbits on dbl_ovrd off deprecated_control off } Block { BlockType Outport Name "Out1" Position [610, 43, 640, 57] } Block { BlockType Outport Name "Out2" Position [610, 118, 640, 132] Port "2" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [15, 0; 0, 5] DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 75] DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Gateway Out" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "blinker" DstPort 1 } Line { SrcBlock "blinker" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "blinker" SrcPort 2 Points [15, 0; 0, -15] DstBlock "Scope" DstPort 2 } } }