Insight "7-Segment LED" Tutorial

1. Start the Xilinx ISE 5.1i Project Navigator
2. Choose File -> New Project
3. Choose a directory for the project. Then set the following options:

   Project Name:	seven_seg
   Device Family:	Virtex2
   Device:	xc2v1000
   Package:	fg256
   Speed Grade:	-6
   Design Flow:	XST VHDL

4. Copy the following files into this directory:
   
   
   • seven_seg.vhd - VHDL Source Code
   • seven_seg.ucf - Top-level Port Definitions
   • seven_seg.mcs - A Dummy PROM data file for insertion into the JTAG chain
5. Choose Project -> Add Source and select the file "seven_seg.vhd". Select "VHDL Module" in the next pop-up window.
6. Choose Project -> Add Source and select the file "seven_seg.ucf".
7. On the left-hand side of the Project-Navigator window, notice the window labeled "Sources in Project:". Make sure the "Module View" tab is selected and select the line labeled "seven_seg (seven_seg.vhd)". This will update the window below, which is labeled "Processes for Current Source:".
8. In the "Processes" window, scroll down and double-click on the line "Generate Programming File". After a few minutes, the file "seven_seg.bit" will be created in this directory.
9. Once the programming file has been generated, you may go back and analyze various aspects of the design
   
   
   • Timing - Choose Synthesize -> View Synthesis Report in the "Processes" window. Scroll down to "Timing Summary". Here you should find the minimum period and a detail of the critical path. The critical path delay is 4.386ns, well below the 10ns maximum for this board.
   • Area - Choose Implement Design -> Map -> Map Report in the "Processes" window. You should see "Number of Slices" close to the top. This is the basic unit of area in the Virtex-II FPGA. This design uses 32 out of 5,120 total slices, so it's pretty small. Scroll down further, and you should find "Total equivalent gate count", which is an estimate of the number of gates if this design had been implemented with standard-cells. This design should have something close to 639 gates.
   • Floorplan - Choose Implement Design -> Place & Route -> View/Edit Place Design or View/Edit Routed Design. These tools show you graphical representations of the physical resources being used on the FPGA. These views can be very helpful to understand what's going wrong if your design was too big or too slow for this FPGA.
10. Make sure that the Xilinx Parallel Cable IV is connected to your computer and to the Insight board correctly.
    
    
    • The plug should be connected to the parallel port.
    • The separate power cable should be connected to a PS/2 mouse port and to the power connector near the parallel port plug.
    • The following 6 signals from the JTAG connector shoud be connected to the insight board: VCC/Vref, GND, TCK, TDO, TDI, TMS.
    • Make sure power is connected to the Insight board through the separate adaptor and that the power is switched on.
11. Start iMPACT. This should be available on the start-menu in Xilinx ISE 5 -> Accessories -> iMPACT.
12. In the "Operation Mode Selection" pop-up window, select "Configure Devices" and click "Next".
13. In the next pop-up, select "Boundary-Scan Mode" and click "Next".
14. In the next pop-up, select "Automaticall Connect to Cable" and click "Finish".
15. Click OK on the "Summary" pop-up.
16. You will be asked to assign a new configuration file for the xc18v04 PROM. Browse to the "seven_seg" project director and select the dummy "seven_seg.mcs" file that you copied here earlier. Click "Open".
17. Next, you will be asked to assign a new configuration file for the xc2v1000 FPGA. Select the "seven_seg.bit" file that you just generated. Click "Open".
18. You will get a warning that the startup clock has been changed to "JtagClk". Ignore this warning for now. Click "OK".
19. NOTE: If iMPACT freezes for any reason during this process, power-cycle the Insight board and choose File -> Initialize Chain to start over.
20. Right-click on the xc2v1000 and select "Program".
21. Click "Ok" on the "Program Options" pop-up.
22. You should see a blue-box with the message "Programming Succeed" and see the seven-segment display on the board couting from 0 to 9. Press the "SW3" button on the board to reset the counter. Press the "SW4" button on the board to pause the counter.
23. Additional resources:
    
    
    • seven_seg.bit - If you don't want to generate it yourself
    • 7-Segment LED Display Reference Design documentation from Insight