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Yan Solihin

Yan Solihin has been awarded $230,229 by the National Science Foundation for research on Beyond Secure Processors - Securing Systems Against Hardware Attacks.

The award will run from September 15th, 2009 to August 31st, 2012.

Research Abstract - Increasing amounts of potentially valuable data are stored and processed in computer system, which motivates increasingly sophisticated attacks to obtain and/or tamper with this information. Protection against such attacks is needed for many important features of secure computing, such as enforcement of copyright protection for content and software, prevention of reverse engineering, trusted distributed computing, and fairness (prevention of cheating) in virtual environments.

One important emerging threat are hardware attacks, which exploit the fact that data can be read or modified directly in the system's memory using devices that dump or scan memory chips. Data transferred along system buses is similarly vulnerable to hardware attacks. These attacks may be more difficult to perform than software-based attacks, but they are also very powerful. A physical attack can bypass all software security protection in the system, allowing attackers to read memory locations that store cryptographic keys and other sensitive information that may be used in software protection schemes. Widely available and inexpensive mod-chips that bypass Digital Rights Management in game systems demonstrate that physical attacks are very realistic threats.

We propose: (1) To conduct detailed investigation into secure booting and configuration mechanisms for secure processors, (2) To explore how secure processors can support system features such as virtualization, virtual memory, inter-process communication, secure I/O communication, and achieve all those with low performance and storage overheads, and (3) To investigate how secure processor technology can be supported in a variety of computer platforms such as single processor systems, mobile systems, and multiprocessor systems with various interconnect topologies.