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A Performance Analysis Framework for the Design of DSP Systems
Ramsey Salim Hourani
Date: 2007-11-27
Degree: PhD - Electrical Engineering
Advisory Committee
W. Rhett Davis - Committee Co-ChairWilliam Edmonson - Committee Member
Winser E. Alexander - Committee Chair
Xun Liu - Committee Member
Zhilin Li - Committee Member
Abstract
The competitive market for generating smaller and faster portable devices compels designers to meet stringent design requirements while keeping time-to-market as low as possible. Application specific integrated circuits and field programmable devices are popular choices for implementing computationally intensive signal processing systems on hardware platforms due to their high speed and low power characteristics. However, the gap between the complex digital signal processing (DSP) algorithm and the efficient hardware implementation continues to grow with the advances in technologies and stringent design constraints. This work presents a performance analysis framework as a method for bridging the gap between the DSP algorithm and the efficient hardware implementation. The work presented in this dissertation focuses on refining a basic DSP algorithm, such as an FIR filter, to several hardware implementations that are closely matched in performance while meeting design constraints. The design methodology in this work uses CAD and EDA tools accepted by both industrial and academic venues. The framework refinement process invokes C++ scripts that efficiently generate and model the DSP algorithms and hardware designs at multiple levels of abstraction. Additionally, scripts within the framework invoke a Synopsys Design Compiler that accurately and efficiently estimates circuit-level performance metrics including area, throughput and power dissipation. This work demonstrated the performance analysis framework using three computationally intensive DSP algorithms as case studies. The first DSP case study focuses on the basic, yet essential FIR filter. Cost functions provided by the framework reduce the design space to a set of efficient hardware designs that meet specific performance metrics. The application of the FIR filter is extended to a slightly more complex DSP algorithm such as an adaptive channel equalizer where the framework methodology is applied to search the design space for efficient equalizer architectures. A more specific DSP algorithm is presented as a third case study where the framework design options allow a designer to select multiple types of optimizations suitable for the hardware implementation of a discrete wavelet transform system. The results of this work illustrate the efficiency in refining a computationally intensive algorithm to synthesizable hardware implementations with minimal effort from the designer.
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