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An Efficient FPGA Implementation of the Discrete Wavelet Transform
Ishita Dalal
Date: 2008-05-15
Degree: MS - Electrical Engineering
Advisory Committee
Dr. W. Rhett Davis - Committee MemberDr. William W. Edmonson - Committee Member
Dr. Winser E. Alexander - Committee Chair
Abstract
Rapid growth in the multimedia and communications industries is fueled by the development of hardware architectures for high performance signal processing algorithms. Implementation of computationally intensive DSP algorithms has become a popular application area for digital hardware platforms such as ASICs and FPGAs. This research is directed towards improving the hardware performance of discrete wavelet transform (DWT) as a case study of DSP application that requires intensive mathematical computations. The DWT is the transformation block used in the latest multimedia compression standards such as the JPEG2000 for still image compression and H.264 for video compression. This work presents the basis for designing an efficient implementation for a multi-level 1-D DWT hardware architecture for use in FPGAs. The proposed architecture systematically combines hardware optimization techniques to develop a flexible DWT architecture that has high performance and is suitable for portable, high speed, power-efficient devices. The hardware optimizations considered include data-interleaving for reduced FPGA resource utilization, polyphase structures for lower power dissipation and pipelining for high throughput applications. Several hardware designs with different combinations of optimizations and filter structures are designed, simulated and synthesized on the Xilinx Virtex-5 FPGA. The impact of these hardware optimization techniques on the overall DWT hardware system are analyzed and the tradeoffs between the pertinent hardware performance metrics: namely power, operating frequency, latency and resource utilization, are investigated. We illustrate that a DWT design using a pipelined and polyphase transpose direct form FIR filter coupled with data-interleaving gives the best combination of the performance metrics when compared to other DWT structures.
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