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Circuit Extraction and Simulation in the presence of Random and Systematic Process Variations
Sunil Basavarajaiah
Date: 2008-08-13
Degree: MS - Computer Engineering
Advisory Committee
Dr. Doug Barlage - Committee MemberDr. Paul Franzon - Committee Member
Dr. Rhett Davis - Committee Chair
Abstract
As CMOS technologies scale beyond sub-90nm process nodes, one of the major hurdles that the CMOS devices face is increasing manufacturing process parameter variations. This has resulted in device characteristics to be more sensitive to these process variations and thus increased the uncertainty in circuit performance parameters like delay and leakage power, leading to loss in parametric yield. The Process Design Kit(PDK) which is an integral part of the design flow needs to enhance the communication across the design-manufacturing interface. This would aid in design for manufacturing, to handle the effect of process variations and result in robust, high performance design. The PDK needs to be variation aware in order to achieve this. This thesis work provides a framework to study and incorporate the effects of random process variations, systematic layout dependent variations, for use with circuit extraction and simulation tools and thus make a PDK variation aware. Modeling the effects of random process variations on circuit performance parameters is done using Response Surface Methodology and Design of Experiments, Statistical Circuit Analysis is carried out with this information. For systematic layout dependent variations, compact model instance parameters due to Well Proximity Effects are extracted according to guidelines from Compact Model Council. An example illustrating the complete flow is presented along with the results from other sample circuits.
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