Contact Information

Address
Campus Box 7911
NC State University
Raleigh, NC 27695-7911


Dr. Doug Barlage

Adjunct Associate Professor

| Education

  1. University of Illinois at Urbana-Champaign
  2. Ph.D. Electrical Engineering (1997)
  3. M.S. Electrical Engineering (1994)
  4. Wright State University
  5. B.S. Engineering Physics (1992)

| Primary Research Interests

  1. Nanoelectronics and Photonics (Including III - V Materials and Devices, Nanotechnology, Silicon Devices and Fabrication)

| Other Research Interests

  1. Electronic Circuits and Systems (Including Analog Circuits, Digital Circuits, Microwave Devices and Circuits)
  2. Power Electronics and Power Systems (Including Power Semiconductor Devices)

| Selected Publications

  1. D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley and R. Chau, High-Frequency Response of 100nm Integrated CMOS tTransistors with high-K Gate Dielectrics, IEDM 2001.
  2. R. Chau, J. Kavalieros, Roberds-B, R. Schenker, D. Lionberger; D. Barlage; B. Doyle, R. Arghavani, A. Murthy, G. Dewey and P. Stokley; 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays, International Electron Devices Meeting 2000. Technical Digest. IEDM IEEE, Piscataway, NJ, USA; 2000; 871 pp. 45-8
  3. D.W. Barlage, J. T.O'Keeffe, J. T. Kavalieros, M.M. Nguyen, R.S. Chau, Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circui, IEEE-Electron-Device-Letters. vol.21, no.9; Sept. 2000; p.406-8.
  4. D.W. Barlage, M. S. Heins, J.H. Mu, M.T. Fresina, D.A. Ahmari, Q. J. Hartman, G. E. Stillman, M. Feng, Ultra low power (
  5. M. S. Heins, D. W. Barlage, M. T. Fresina, D. A. Ahmari, Q. J. Hartmann, G. E. Stillman and M. Feng, Low phase noise Ka-Band VCOs using InGaP/GaAs HBTs and coplanar waveguide, 1997 IEEE MTT-S International Microwave Symposium.

| Awards and Honors

  • 2006 - NSF Career Award
  • 2002 - MIT TR 100, One of 100 outstanding innovators under the age of 35 class for key contributions in the demonstration of 30nm gate length transistors
  • 2001 - Intel Divisional Award "World's first sub-70nm Depleted Substrate Transistor"
  • 2000 - Intel Corporate Achievement Award (2000) "For the demonstration of 30nm CMOS transistors with world record performance"
  • 2000 - Intel Divisional Award "World Record CMOS performance with 30nm transistors"
  • 1999 - Intel Divisional Award "High Yield Dual Gate Oxide Coppermine CPU"
  • 1998 - Gate Oxide Methodology
  • 1996 - Intel Foundation University Fellowship (1996-97)
  • 1992 - Outstanding Student - Engineering Physics 1992
  • 1992 - Wright State University Suma Cum Laude
  • 1990 - Wright State Presidential Scholar 1990-91
  • 1989 - Outstanding Physics Student - 1988-89 (Top Grade in University for Sophomore Physics)
  • 1988 - Wright State Honors Scholar 1988-1992