Contact Information

Address
Campus Box 7911
NC State University
Raleigh, NC 27695-7911


Dr. Lei Luo

Adjunct Assistant Professor

| Biography

Lei Luo is a design engineering manager and principal engineer with Rambus Inc., working on high-speed & low-power advanced serial link and memory interface design. He received the Ph.D degree from NC State University in electrical and computer engineering in 2005. His research interests include micro-architecture, mixed-signal circuit design and signal/power integrity for advanced I/O design as well as signal processing techniques for communications. He has over ten US patents pending on high speed serial link and memory interface design.

| Education

  1. 2005 - Ph.D in ECE, NCSU
  2. 2001 - MS Southeast University, Nanjing, China
  3. 1998 - BS Southeast University, Nanjing, China

| Selected Publications

  1. Luo, L.; Wilson, J.; Mick, S.; Xu, J.; Zhang, L.; Franzon, P. “3Gb/s AC Coupled Chip-to-Chip Communication using a Low Swing Pulse Receiver”, IEEE Journal of Solid-state Circuits, Vol. 41, No. 1, Jan. 2006, pp. 287 - 296.
  2. Luo, L.; Wilson, J.; Mick, S.; Xu, J.; Zhang, L.; Franzon, P. “3Gb/s AC Coupled Chip-to-Chip Communication using a Low Swing Pulse Receiver”, International Solid-State Circuits Conference, Dig. Tech. Papers, 2005, pp. 522-523.
  3. Luo, L.; Wilson, J.; Mick, S.; Xu, J.; Zhang, L.; Erickson, E. and Franzon, P.; “A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver”, IEEE CICC 2006.
  4. Luo, L.; Wilson, J., Xu, J.; Mick, S.; and Franzon, P. “Signal Integrity and Robustness of ACCI packaged systems”, IEEE Electric performance on Electronic packaging, pp. 11-14, Oct. 2005.
  5. Zerbe,J.; Daly B.; Luo, L.; Stonecypher B.; Dettloff W.; Eble J. and Stone T. “A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for Low Power Interfaces”, IEEE Journal of Solid-state Circuits, Jan 2011.
  6. Dettloff, W.; Eble J.; Luo L.; Kumar P.; Heaton F.; Stone T. and Daly B. “A 32mW 7.4Gb/s Protocol-Agile Source-Series-Terminated Transmitter in 45nm CMOS SOI”, IEEE International Solid-State Circuits Conference, Dig. Tech. Papers 20-6, 2010, Feb.2010.
  7. Zerbe,J.; Daly B.; Luo, L.; Stonecypher B.; Dettloff W.; Eble J. and Stone T. “A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for Low Power Interfaces”, IEEE Symposium on VLSI Circuits, 2009.
  8. Mick, S.; Luo, L.; Wilson, J.; Franzon, P. “Buried Bump and AC Coupled Interconnection Technology”, IEEE Transactions on Advanced Packaging, vol. 27, No. 1, pp. 121–125, Feb. 2004.

| Awards and Honors

  • 2008 - DesignCon Paper Award
  • 2007-2011 - RAMBUS annual Inventor award
  • 2005 - "Intel Best Student Paper Award”, IEEE, Electrical Performance of Electronic Packaging Conference
  • 2004 - 1st place, NCSU ECE Graduate Student Seminar Competition