Memory Systems / Memory Management

Computer Architecture and Systems

The Memory Subsystem is an important component in uniprocessor and multiprocessor systems. It consists of temporary storage that is managed by hardware (cache) or software (scratchpad), as well as more permanent storage that is volatile (main memory) or non-volatile (Flash memory, disk, etc.). It consists of on-chip storage as well as off-chip storage.

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The importance of the role of the memory subsystem on the overall system performance has been growing in the past few decades and is expected to grow even more in the future. Recognizing such growing importance, increased design focus on the memory subsystem has led to caches taking up a larger fraction of die area. Already, caches take up more than 50% of the die area of some high performance microprocessors. In future multicore and manycore processors, the die area allocated for caches will likely increase even more.

Designing the memory subsystem is challenging because it involves balancing among multiple goals. The goals include fast access time, programmability, high bandwidth, low power, low cost, reliability, and security. Some of the goals may contradict one another, thus it is important to strike a good balance given the target market of a system. For example, techniques to hide memory access latency such as prefetching tend to increase bandwidth consumption. Techniques to reduce bandwidth consumption such as cache and link compression tend to increase the cache access latency. Techniques for improving reliability such as parity and error correcting code tend to increase the cost, access latency, and bandwidth consumption. Techniques for improving programmability such as cache coherence increase cost and power consumption. Therefore, in designing the memory subsystem of a computer system, extensive knowledge and expertise, as well as careful attention to the target market and practical design constraints, is crucial to success.

At North Carolina State University, we provide extensive education and training in the area of memory subsystem. Memory subsystem is covered in courses ranging from the undergraduate level, introductory graduate level, and even at the advanced graduate level. Our research program is at the cutting edge of innovation in the memory subsystem, and is recognized internationally. We have a tradition of spearheading research activities in new areas, identifying new problems and proposing innovative solutions to such problems. Some examples of our past projects that have demonstrated our role in pioneering research effort in memory subsystem include:

  • Fair caching : a new concept in which when a cache is shared by applications running on multiple processor cores, the effect of contention on performance is equalized among all cores.
  • Multicore Quality of Service : a framework for providing performance guarantee to applications running on a multicore chip. when multiple processor cores on a chip share a common memory hierarchy, it is important to provide performance isolation (better yet, performance guarantee) to different cores to achieve. It is also crucial that providing Quality of Service does not penalize the system throughput. The project focuses on both providing Quality of Service and optimizing throughput in such an environment.
  • Encrypted memory : memory system that is encrypted and authenticated. Plain text of data and code stored in the main memory and disk is vulnerable to an attacker who tries to obtain secret information stored in the memory. To protect against the possibility of such attacks, the memory can be encrypted and protected with authentication code. The project achieves secure memory with low performance overheads and compatibility with modern system features such as virtual memory and inter-process communication.
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