Franzon Explores Ways to Reduce Cost of RFID Chips
Dr. Paul Franzon, professor of electrical and computer engineering, has been awarded $445,713 by the National Science Foundation (NSF) for research on AC Powered Digital Circuits, specifically exploring ways to reduce the cost of RFID chips by eliminating most of the circuitry needed for managing the recovered power on the chip.
Posted on Friday, October 24, 2014 | Filed Under: News
Dr. Paul Franzon, professor of electrical and computer engineering, has been awarded $445,713 by the National Science Foundation (NSF) for research on AC Powered Digital Circuits, specifically exploring ways to reduce the cost of RFID chips by eliminating most of the circuitry needed for managing the recovered power on the chip. This has potential to reduce the chip cost by about one-third.
Dr. Paul FranzonRFID chips are at the core of the tags stores typically attach to clothing and high end items – though they have a lot more uses beside this. The main technique employed in this project is to directly operate the circuits from the recovered wireless power. A new chip design technique has been identified for doing this and will be exploited and further explored in the project. This technique also has potential to increase the range at which the RFID tag can be powered. A successful outcome will open new market opportunities to use RFID.
At the core of this proposal is a new circuit structure, one that permits digital and some analog operations to be performed from an AC, rather than DC, power supply. Unlike previous AC powered circuit concepts the proposed concept can be powered from RF sources up to approximately the unity gain frequency of the device technology at that operating voltage. Thus, and of particular interest application-wise, this circuit structure will work well at Gen2 EPC RFID frequencies in the 860 to 960 MHz range.
The state of the art for RFID generally requires that 25% to 33% of the circuit area be given over to RF-DC power conversion and provides for conversion efficiencies in the 25% to 50% range. In comparison, the proposed circuit structure enables RFID chips to be built with almost no conversion overhead and with very high conversion efficiency.
In turn, these technological capabilities enable new and interesting applications. RFID has always been challenged to meet the ultra-low cost requirement once dictated by Walmart. While the proposed innovation does not lead to a 2 cent tag, it has potential to reduce the silicon tag area by around 25%, which in turn leads to a tag cost reduction of 10%. Another variant of this technology permits tags to operate at high efficiency and thus low RF or magnetic power levels. As well as investigating low-cost and low-power operation, we will investigate the potential of this technology to be an RFID sensor suited to solving the cold-food chain sensing problem.
The award will run from August 1st, 2014 to July 31st, 2017.