of High Speed Digital Circuits and Package-Level Interconnect
is the first in a series that will be made available on this server.
The design of high speed digital circuits and interconnect is a complex
task. The main hurdle in performance optimization of high speed circuits
is the difficulty in modeling the circuit performance. Analytic modeling
of performance is difficult and inaccurate. The best prediction of performance
is obtained from running a circuit simulation program. However, circuit
simulation is computationally expensive. There is a need to obtain accurate
performance models, based on circuit simulation, that can be employed for
design. The performance models are established before detailed design commences,
and can be employed across multiple designs executed in the same technology.
In this thesis, circuit performance as predicted by simulation, is captured
in a stochastic model which is employed in a highly interactive optimization
program to generate very good circuit designs with few runs of the circuit
simulator. The interconnect synthesis problem is managed by establishing
the interconnect performance through an novel experimental design technique.
The interconnect performance is estimated at design time by interpolation
on the simulated designs. A global routing technique is presented whereby
performance constraints and routing congestion are simultaneously managed.
The global routing results are employed to generate design rules for a
detailed router, so that performance constraints are satisfied. The combination
of performance modeling, global routing and rule generation provides a
complete solution path for the synthesis of high speed interconnect on
MCMs and PCBs with few routing layers to meet tight performance constraints.
(Under the supervision of Dr. Paul D. Franzon)